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PCB Trace Spacing Calculation for Voltage Levels

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PCB Trace Spacing Calculation for Voltage Levels CALCULATING SPACING BETWEEN PCB TRACES FOR VARIOUS VOLTAGE LEVELS CIRCUIT BOARD LAYOUT GUIDELINES Proper distances between PCB traces are hair-trigger to stave flashover or tracking between electrical conductors. Unfortunately, there is no single solution to this issue. There is a variety of industry and safety standards that prescribe variegated spacing requirements depending on the voltage, using and other factors. Here I am providing some considerations and a simple widget that will help you determine the proper spaces between PCB tracks. Home Tutorial Topologies SMPS diamond Thermal diamond Software PCB diamond Computer PSU UPSSpinTransformers Formulas EE Reference Inverters Generators Solar SAFETY REQUIREMENTS When a product has to be recognized by a unrepealable safety agency, there may be a legal requirement to meet specific insulations listed in the relevant agency's standard. In this case, finding the required spacing is increasingly or less straightforward. For example, in the U.S. for most mains-powered or battery-powered information technology equipment, the minimum unliable PCB spacing should be unswayable from IEC/UL 60950-1 2nd Edition Tables 2K, 2L, 2M or 2N. These tables specify so-called clearance and "creepage" distances for various grades of insulation as functions of working voltage, pollution degree, PCB material group and coating. The required grade depends on the location of the circuit. The standard specifies functional, basic, supplementary, double and reinforced insulations. For example, when a dispersal can create a hazardous voltage on user wieldy conductive parts (such as in specimen of insulation between mains circuits and low-voltage secondary circuits), a double or reinforced insulation is required. In this case, to separate such circuits on the PCB you need to double the respective distances shown in an towardly table. The diagram unelevated illustrates the clearance and creepage measurements. It lists as an example the requirements (in mm) for a typical using with AC mains 250Vrms, peak working voltages under 420V, and peak AC mains transients up to 2.5kV. Note that 1 mm ≈ 40 mils. If you don't have an wangle to the UL document, this creepage calculator will help you find the necessary distance. Of course, you should consult with UL 60950-1 or an workable standard for final diamond decisions. Note that for the equipment manufactured in China and intended for use at altitudes whilom 2,000m (up to 5,000m), equal to GB 4943.1-2011 the minimum distances has to be multiplied by 1.48. OPERATIONAL REQUIREMENTS The distances provided by IEC and UL unquestionably profoundly exceed the spacing necessary just for proper operation of the devices. This was washed-up in order to provide increased protection versus electric shock. For the circuits whose locations do not require electric shock protection, spacing between printed spin tracks can be made smaller. For the so-called functional insulation, UL 60950-1 permits to use separation distances lesser than the specified in their charts. They just have to withstand the electric strength test (casually tabbed HiPot) per Par.5.2.2 Table 5B. In other words, where only functional insulation is required, you don't need to meet any specific clearance between PC traces for as long as there will be no electric dispersal between them at the prescribed test voltage. The latter often is several times greater than very working voltage between separated traces. Unfortunately, there is no well-spoken information in the literature on what is very dispersal voltage between the conductors and how to diamond a PCB to pass a specific HiPot. Experiments performed by UL in the undertow of wringer of silver PCB surface finish, demonstrated that the withstand voltage of a pair of parallel conductors is purely a function of the spacing rather than surface finish. Based on the experiments, UL specified withstand voltage of 40 volts/mil or well-nigh 1.6 kV/mm in their UL796 Standard for Printed Wiring Boards. In my view, it is reasonable therefore to use these numbers in designing the workbench to withstand a particular test. For example, for working voltage 500V in secondary circuits you need to withstand 1740 Vrms per UL 60950-1 Table 5B Part 2. Such sinewave has 1740*√2=2461 V peak value. With the 40V/mil criterion, the required minimum loftiness would be 2461/40=62 mils (or 1.6 mm). Voltage (DC or AC peak) SPACINGmminches IPC-2221B: external internal coated IPC9592 For products that are not covered by UL60950-1 safety standard, to determine the electrical clearances the designers normally consult with IPC-2221. It is widely wonted throughout the world as a generic PCB diamond standard for commercial and industrial applications. The Table 6.1 of IPC-2221B specifies minimum required usherette clearances as a function of voltage, elevation level and the coating. Since their introduction in 1998, these numbers were never revised. IPC just widow the values in inches in revision A and left them unchanged in rev.B. Of course, it is unchangingly desirable to maximize whenever possible the loftiness between tracks on individual layers to minimize the possibility of electric breakdown, reduce parasitic capacitance, and simplify PCB assembly. However, considering of usual shortage of space, spreading out the traces and components increasingly than it is really necessary may not be feasible. From a technical standpoint, IPC stepwise clearance limits are mostly baseless. For example, there is no reason whatsoever, why you need 2.5mm for 301V, while for 300V you can use 1.25mm. An IPC-9592 standard for power conversion circuits originally provided linear functional spacing requirements: SPACING (mm) = 0.6+Vpeak×0.005. Linear function of undertow makes increasingly sense. However, in most cases the whilom formula resulted in plane higher spacings and in grossly over-designed spin board. Later revisions of this document returned to a sort of step function and relaxed the requirements at the low end: 0.13mm for V<15V, 0.25mm for 15V≤V<30V and 0.1+V×0.01 for 30V≤V<100V (for uninsulated conductors). Our widget provides rounded numbers based on the whilom equations. One would think that a unstipulated PCB diamond standard has to be increasingly liberal than UL requirements. In reality, for V>150V IPC unquestionably calls for larger spacings between uncoated external conductors than those you can derive from UL 60950-1 Table 5B in conjunction with the 40V/mil criterion. Note that often all IPC doc's are voluntarily rather then mandatory. Particularly, they state that "Existence of such Standards and Publications shall not in any respect preclude any member or nonmember of IPC from manufacturing or selling products not conforming to such Standards and Publication". Where shortage of space on a PCB is an issue, for non-UL applications you may need to use the spacing smaller than those that are prescribed by IPC. However, be sure to use an zaftig safety factor to withstand the voltages substantially higher than the peak voltage between the copper traces under any unwont and transient conditions. It is interesting to note that many major power supply manufacturers in their low-power off-line designs are widely using 500-800V MOSFETs in TO220 package operating at 400V and higher. With this package you can get well-nigh 30 mils spacing between the pads, while the documents would require at least 100 mils.Planeif you spread the leads on the PWB, you can't do anything with 50-mil spacing between the TO220 leads withal the surface of the package. As a reference, the orchestration unelevated compares PCB loftiness limits based on the pursuit three specs for external layers of uncoated yellowish boards; IPC2221B IPC9592B; UL60950 for functional insulation in secondaries, designed to meet the test per Table 5B with the theorizing of 40V/mil withstand voltage. Note the curves unelevated are for functional (not safety!) insulation. CONCLUSION When the product is covered by an UL standard, you need to select the towardly table in the UL standard. Particularly, for the products covered by UL60950-1, determine the grade of insulation depending on the location of the circuits and then find from Tables 2K-2N minimum required spacing based on working voltage, pollution degree, PCB material group and the coating. For functional insulation UL permits usage of lesser loftiness if it withstands the test voltage per Table 5B. For practical purposes, in my view, you can summate the loftiness on the theorizing that the spin workbench withstands 40V/mil (1.6kV/mm). Of course, this test voltage is unchangingly much higher than very operating voltage. Also note that technically the insulation requirements given in UL 60950 are for frequencies up to 30 kHz. So far, both 60950-1 2nd Edition and IEC 62368-1 permit the same requirements for frequencies whilom 30 kHz until they will icon out what to do well-nigh it. You can't rule out that in the future IEC and UL would prefer tougher standards for upper frequency circuits based on IEC 60664-1 and IEC 60664-4, which would have a major effect on most SMPS designs. If there is no legal requirement to meet UL or any other product tenancy law, try using IPC-2221B (or IPC-9592B for power circuits) loftiness recommendations whenever possible. However, where shortage of space on a PCB is an issue, you may need to segregate a smaller spacing, provided it still withstands test voltages substantially higher than the peak voltage between the traces. The whilom wringer takes into worth only electrical dispersal issue. There are other criteria that should be considered when selecting electrical clearance, such as conductor's temperature rise. Also see unstipulated guidelines for printed spin workbench design, layout rules for power circuits, and signal integrity issues. LEGAL. The information provided here reflects only a personal opinion of the tragedian and does not constitute a professional or legal advice. It is not intended to substitute official standards-- consult them for all final decisions. Also see our unstipulated Disclaimer linked below. Disclaimer, Disclosure and Terms of Use | Contact Us |Well-nighUs | Privacy ©2009, 2014 Lazar Rozenblat