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PCB Layout Guidelines and Tips

smps.us
This tutorial provides guidelines, rules and tips for PCB layout of power circuits, as well as basic info on safety regulations.
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Keywords cloud circuit PCB design power ground circuits control current traces board µF routing supply guidelines software IPC components spacing trace SMPS
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circuit 11
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design 9
power 8
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Tutorial
Power Supply Tutorial- SMPS
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SMPS Power Supply Topologies: Comparison and Selection
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SMPS Design: Switching Power Supply Circuits and Schematics
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Heat Sink Design, Calculators, Thermal Analysis Software
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Electronic Circuit Simulators and Design Software
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PCB Printed Circuit Board Design Guide
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Computer Power Supply- ATX Pinouts, Schematics, Reviews
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Uninterruptible Power Supply (UPS): Review and Buying Guide
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Power Transformer & Inductor Design
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Electrical Formulas, Calculations, Basic Electronics Engineering Reference
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Electrical Engineering Information Online: Formulas and Theorems
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Power Inverter Circuits: DC-AC Converter
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Unitrode / TI Power Supply Design Seminar Archives
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Glossary and Definitions of SMPS and Power Electronics Terminology
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quiz
Power Supply Safety Quiz
connectors and pinouts
ATX 24-pin Power Supply Connector with 20-pin Board & Visa Versa
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PCB Layout Guidelines and Tips
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PCB Trace Spacing Calculation for Voltage Levels
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PCB Layout Guidelines and Tips A TUTORIAL ON PRINTED CIRCUIT BOARD (PCB) LAYOUT THE GUIDELINES FOR SWITCHING POWER SUPPLIES (SMPS) DESIGN A shielding PCB layout is hair-trigger for proper operation of power electronics devices. While routing of tenancy circuits can be washed-up by an wheels routing pcb software, hair-trigger power circuits should be placed by hand. This tutorial provides you with some guidelines and tips. 1. High-frequency spin diamond requires shielding grounding. The "ground" in a spin is supposed to be at one potential, but in reality it is not. When currents spritz through traces which have non-zero impedance, voltage differences will occur at variegated points withal the ground path. To minimize these voltages use ground plane for tenancy circuit. Try to make most of ground connections through vias to this plane rather than through PC traces. 2. For each power supply stage, alimony power ground and tenancy ground separately. Tie them together [If they are electrically connected] in one point near DC output return of the given stage. 3. If you use a multilayer printed spin workbench with surface mount components, place tenancy ground plane on an inner layer so that it acts as a shield between power and tenancy circuits. 4. Minimize areas and lengths of the loops which contain upper frequency switching currents. 5. Place capacitors that shirk bias supply voltages and reference pins (if any) of all ICs physically tropical to the respective pins. For suburbanite fries use a combination of a large capacitor (10 µF - 100 µF) and a small ceramic capacitor (0.1 µF - 1.0 µF). 6. Place filter capacitors so that their leads physically go right into the printed spin workbench traces that siphon mainstream of the current to be filtered. 7. If you parallel power semiconductors, try to use symmetrical routing with equal usherette impedances for each of the paralleled devices. 8. Try not to place routes under power transformers and EMI chokes. 9. Choose the width of PCB traces based on winning temperature rise per IPC2152 at the rated current, as well as winning DC and AC impedances. Also, make sure that the trace will not fuse at any unwont current (such as short spin current) that could develop in the spin surpassing a electronic protection activates or a fuse clears. 10. The distances between various circuits should be unswayable equal to the requirements of workable standards. For example, for the product covered by UL 60950-1 2nd Edition the creepage and clearance from primary circuits to secondary circuits and safety ground should be unswayable from the Tables 2K through 2N of this standard. In a typical commercial using with 120/250 VAC input, creepage between primary and low-voltage secondary circuitry per UL/IEC 60950 should be 6.4 mm minimum. For increasingly details see our guide to PCB trace spacing. 11. For spin spacing in non-UL applications you can often use the recommendations of Table 6-1 of IPC-2221B. It is a generic standard for PCB diamond which replaced old IPC D-275. The recommended spacings for power supply circuits is given by IPC-9592B. In my view, the whilom IPC guidelines are too conservative. Note that all IPC standards are voluntary rather then mandatory. 12. Schematic diamond and PCB layout are often washed-up by variegated engineers. A PCB designer usually does not know the details of the SMPS spin operation and criticality of components location. In this case, the electrical engineer should provide this information to the spin workbench designer, help set diamond rules and closely supervise the routing process. Professional schematic capture software allows you to set various constraints for specific nets or groups of components. Particularly, you can specify minimum line width, net spacing type, and plane maximum and relative signal propagation delays. For increasingly spin workbench layout guidelines, self-ruling software and diamond aids see our PCB diamond tutorial and trace width numbering tool. Home | Tutorial | Topologies | SMPS diamond | Software | PCB diamond | Computer PSU | UPS |Spin| Transformers| Formulas | EE Reference | Inverters | Thermal diamond | Generators | Solar Disclaimer, Disclosure and Terms of Use | Contact Us | About Us | Privacy ©2003, 2011-2015 Lazar Rozenblat